PTL1 discloses a production method for a three-dimensional memory cell array. More specifically, PTL1 discloses a method of forming a hole in a multilayer film including electrically conductive layers and insulative layers stacked alternately and repeatedly in a predetermined number of cycles so that the hole extends through the electrically conductive layers and the insulative layers. An insulative film having an ONO (Oxide-Nitride-Oxide) structure including a silicon nitride film sandwiched between a pair of silicon oxide films is provided on an inner peripheral surface of the hole, and a silicon pillar is embedded inside the hole. The silicon pillar functions as a channel, while the electrically conductive layers each function as a control gate. With this arrangement, a plurality of memory cells are provided which are isolated from each other by the insulative layers in the depthwise direction of the hole. The memory cells are each capable of accumulating electric charges in the insulative film of the ONO structure to store information.